Applications of CFD tools in PCB, Board-level and Chassis Level Thermal Simulations
There are vast range of applications of thermal simulations in electronics industry dealing with Printed Circuit Board (PCB). In addition to board and chassis level simulation, thermal management of data centres include specialized cooling methods like heat sinks, TEC (Thermo-Electric Cooling), heat pipes, PCM (Phase Change Material), heat spreaders... A thermal network model for MOSFET-on-PCB is shown below.
The thermal network is a reasonably accurance and extermely fast approach to evaluate casing temperature of heat generating devices.
Equivalence of Radiative Heat Transfer Rate at Low Temperature and Small Temperature DifferencesConvective heat transfer rate: qCNV'' = h x [T - TREF].
Radiative heat flux rate: qRAD'' = ε x σ x [TW14 - TW24] = ε x σ x [TW1 - TW2] x [TW1 + TW2] x [TW12 + TW22]
Comparing the two equations: hRAD ≡ ε x σ x [TW1 + TW2] x [TW12 + TW22]For ε = 1.0, TW1 = 100 [°C] and TW2 = 40 [°C], hRAD = 9.23 [W/m2.K]
For ε = 1.0, TW1 = 80 [°C] and TW2 = 40 [°C], hRAD = 8.41 [W/m2.K]
For ε = 1.0, TW1 = 60 [°C] and TW2 = 50 [°C], hRAD = 8.01 [W/m2.K]
As you can see, the convective heat transfer coefficient in natural convection with air ranges between 5 to 15 [W/m2.K]. Hence, the contribution of radiation in natural convection cases (such as electronic cooling) is approximatly equal to the convective heat transfer rate. In other words, convection and radiation contribute almost equal in natural convection heat transfer cases dealing with low temperature differences.
Die: It designates the piece of semiconductor on which all the active circuits lie. Dies are made of Silicon (110 – 150 W/m.K) or Gallium Arsenide (GaAs, 45 – 60 W/m.K) is used in special applications such as microwaves. The circuitry is present within a thin layer on one side only, known as active surface. The concept of "junction temperature" applies to the top surface of the die. The heat flux in the die and die-attach is very high, the junction temperature is very sensitive to the thermal conductivity and the thickness of the die and die-attach.
The Die is often attached to the substrate or the die pad by an adhesive known as the "die attach" which is made of an epoxy based compound having thickness 0.025 - 0.050 [mm] and thermal conductivity in the range 1 - 2 [W/m.K]. The semiconductor material of a die has a conductivity approaching that of a metal. If the active layer is assumed to generate constant power per unit area (an assumption that may not always be valid), the die will be practically isothermal. In practice, applications exist for which the heat flux varies significantly across the die, in which case a temperature gradient may exist on its active surface. For most packages, the thermal resistance offered by the die is small in comparison with that offered by the rest of the package. Referecnce: FloTHERM Pack User's Guide
Due to low thickness of the "die attach", it causes very little heat spreading. At the same time, it offers significant thermal resistance in out-of- the-plane direction due to its poor thermal conductivity value. Si is very widely used because of its cheap price, easiness in processing and fairly high thermal conductivity. SiC is an alternative material [though very costly] that has high thermal conductivity of 370 [W/m-K].
Die Pad or Die Flag: The Die is placed in insulated boxed often plastic packages, on a thin metal plate (made of copper and larger than the die) known as the die flag or die pad. It helps both in the manufacturing and thermal (heat dissipation) function. The metallic die flag acts as an effective heat spreader due to very high thermal conductivity of copper which can reduce the thermal resistance of a package by up to 15%.
Bond wires, made of Gold or Aluminum having diameter of the order of 0.025 [mm], are characteristics of wire-bonded packages. The number of bond wires in an IC package are of same order as the number of external leads/pins. Excerpts from "FloTHERM Pack User's Guide": In most ceramic packages, a negligible portion of the heat from the Die flows to the substrate through the bond wires. However, in plastic packages this may not be the case. Bond wires play a significant role in the heat transfer within peripheral leaded packages such as the PQFP. In area-array plastic packages such as the PBGA, bond wires can be important, especially for a 2-layer substrate.
Encapsulant: Also known as 'Overmold', it is an epoxy based compound with a thermal conductivity 0.6 - 0.7 [W/m.K].
Reference: FloTHERM PACK User GuideCBGA = Ceramic Ball Grid Array, PBGA = Plastic Ball Grid Array, TBGA: Tape Ball Grid Array, CPGA: Ceramic Pin Grid Array
Thermal conductivities: Alumina - 21 [W/m-K], Kovar - 17 [W/m-K], Typical encapsulant and elastomer material - 0.4 ~ 0.6 [W/m-K], Polyimide: 0.2 [W/m-K], 37Pb/63Sn solder: 50 [W/m-K]
In general, thermal resistance Θ or RTH = ΔT / P where P is power dissipation from the chip package in [W] and ΔT = TJ - TA.TJ is the junction temperature and TA is the ambient temperature. In other words, the thermal resistance of an IC package is defined as the amount of heat generated or a rise in temperature when 1 [W] of power is dissipated in the IC. E.g. if an IC package generate 0.50 [W] with Junction-to-Ambient thermal resistance of 100 [K/W], the temperature of junction will rise by 0.5 [W] × 100 [K/W] = 50 [K] over the ambient. The construction of IC packages decides the thermal resistances: few types are Dual Inline Packages (DIP), Ceramic through-hole package, Plastic through-hole package, Plastic leaded chip carrier (PLCC), Quad Flat Package (QFP), Plastic dual construction surface mounte package, Thin small outline package (TSOP)...
The standard test conditions are specified by Joint Electron Device Engineering Council (JEDEC) such as JESD15-3: Two-Resistor Compact Thermal Model Guideline, JESD51: Methodology for the Thermal Measurement of Component Packages (Single Semiconductor Device) and JESD51-12: Guidelines for Reporting and Using Package Thermal Information.
Example Calculation - 1: A transistor with power rating of 10 [W] and internal thermal resistance of 1.5 [K/W] has a case temperature of 60 [°C]. What is the actual value of junction temperature?Here:
Example Calculation - 2: A chip with 5 [W] rating has a maximum junction temperature of 120 [°C] and an internal resistance of 0.5 [K/W] at an ambient of 40 [°C] with aluminium oxide wafers. What is the maximum permissible thermal resistance of the heatsink?
Excerpts from "Semiconductor and IC Package Thermal Metrics" by Texas Instruments: RΘJA is a variable function of not just the package, but of many other system level characteristics such as the design and layout of the PCB on which the part is mounted. In effect, the test board is a heat sink that is soldered to the leads of the device. Changing the design or configuration of the test board changes the efficiency of the heat sink and therefore the measured RθJA. In fact, in still-air JEDEC-defined RΘJA measurements, almost 70 ~ 95% of the power generated by the chip is dissipated from the test board, not from the surfaces of the package. Because a system board rarely approximates the test coupon used to determine RΘJA, application of ΘJA using
[TJ = TA + RΘJA × P]results in extremely erroneous values.
The document further elaboarates: "In light of the fact that RΘJA is not a characteristic of the package by itself but of the package, PCB and other environmental factors, it is best used as a comparison of package thermal performance between different companies. For example, if TI reports an RΘJA of 40 [°C/W] or 40 [K/W] for a package compared to a competitor's value of 45 [K/W], the TI part will likely run 10% cooler in an application than the competitor's part." As a "margin of safety", the permissible limit of junction temperature should be reduced by 20-30 [°C] from the value specified by the manufacturers.
Excerpts from "Thermal Design Basics" by Analog Devices: In ICs, one temperature reference point is always the device junction, taken to mean the hottest spot inside the chip operating within a given package. The other relevant reference point will be either TC - the case of the device, or TA - that of the surrounding air. This then leads in turn to the above mentioned individual thermal resistances ΘJC and ΘJA. Taking the most simple case first, ΘJA is the thermal resistance of a given device measured between its junction and the ambient air. This thermal resistance is most often used with small, relatively low power ICs such as op-amps, which often dissipate 1 [W] or less. Generally, ΘJA figures typical of op-amps and other small devices are on the order of 90-100 [°C/W] for a plastic 8-pin DIP package, as well as the better SOIC packages.
Reference: MOSFET power losses and how they affect power-supply efficiency - by By George Lakkas, Product Marketing Manager, Power Management
MOSFETs have a finite switching time, therefore switching losses come from the dynamic voltages and currents the MOSFETs must handle during the time it takes to turn on or off. MOSFET switching losses are a function of load current and the switching frequency of power supply. There are 3 types of losses: conduction losses, switching losses and static (quiescent) losses.
Most of the power is in the MOSFET gate driver. Gatedrive losses are frequency dependent and are also a function of the gate capacitance of the MOSFETs. When turning the MOSFET on and off, the higher the switching frequency, the higher the gate-drive losses. This is another reason why efficiency goes down as the switching frequency goes up.
Reference: "Enhance Reliability of Semiconductor Devices in Power Converters by Minh Hoang Nguyen and Sangshin Kwak" - IGBT and SiC MOSFET have a similar chip-level structure, except for an additional p+ layer above the collector in IGBT and an additional body diode part in SiC MOSFET.
Reference: AN90003 - LFPAK MOSFET thermal design guide
The conventional single side cooling 5x6mm MOSFET called SOP Advance (Figure 1) is covered with an insulating mold. Therefore, the heat dissipation path of the package is mainly its bottom drain side cooling plate.
The DSOP Advance package has a top source side cooling plate in addition to the bottom drain side plate as shown in Figure 2. These cooling plates contribute in reducing the thermal resistance (Rth).
At thermal equilibrium, the maximum power dissipation PDMAX of a power MOSFET can be expressed in terms of the ambient temperature TA, the maximum channel temperature TCHMAX of the MOSFET and the channel-to-ambient thermal resistance RTHCH-A
Reference: Numerical Study on Heat Transfer Characteristics of the 36V Electronic Control Unit System for an Electric Bicycle by Gihan Ekanayake, Mahesh Suresh Patil, Jae-Hyeong Seo and Moo-Yeon Lee.
|Component||Material||Thermal Conductivity [W/m-K]||Density||Specific Heat Capacity [J/kg-K]|
|MOSFET||Silicon||80 ~ 150*||2390||712|
A PCB trace is a thin line of conducting copper placed on a non-conductive base material usually called FR4 that carries the signal and power to the whole circuit. A copper trace has a specific width called trace width, and a particular thickness. The thickness of PCB is specified in ounce/ft2 = 28.35 gm/ft2 = 0.3052 [kg/m2] = 0.3042/8900 = 3.43 x 10-5 [m] = 0.0343 [mm]. For typical PCBs, the most common copper thickness is specified as 35 [μm] which is equivalent to 1.0 [oz/ft2]. With electrical resistivity of 1.72 x 10-8 [Ω.m] at 25 [°C] for copper, the electrical resistance per inch width per meter length of copper trace is 0.02 [Ω]. The electrical resistance per inch width per inch length of copper trace would be 0.50 [mΩ]. The resistance value shall increase in direct proportion of the length and inverse proportion of the width and/or thickness (mm or oz/ft2).
For example, electrical resistance per inch width per inch length of copper trace having thickness of 2.0 [oz/ft2] would be 0.50 / 2 = 0.25 [mΩ]. Electrical resistance per 0.1 inch width per inch length of copper trace having thickness of 2.0 [oz/ft2] would be 0.50 / 2 / 0.1 = 2.5 [mΩ]. Electrical resistance per 0.1 inch width per meter length of copper trace having thickness of 1.0 [oz/ft2] would be 0.50 * 39.37 / 0.1 = 0.197 [Ω].
With temperature coefficient of electrical resistance 0.0039 [1/K], electrical resistance per 0.1 inch width per meter length of copper trace having thickness of 1.0 [oz/ft2] at 100 [°C] would be 0.197 x [1 + 0.0039 x 75] = 0.255 [Ω]
Trace Heating: In the electrical wires the cooling rate initially increase with thickness of insulation, reaches a peak and then starts decreasing. Similarly, the temperature of traces are dependent on the board thickness, traces on top of a thin board get hotter than one on a thicker board. This is because a thicker board has higher cross-section for the heat to conduct through. Beyond a thickness of board, there is more material under the trace than the trace can efficiently utilize - the path to surface on which convection occurs gets longer - and hence there is no improvement in temperature or in fact the temperature of traces may increase further. PCB trace temperatures are very sensitive to thermal conductivity though the in-plane thermal conductivity has higher influence than through-plane value.
There are many programs used to generate design of electronic items such as PCB and chips. Cadence, EasyEDA, Eagle, Altium Designer to name few. However, there is a need to have interface between ECAD and MCAD. This is accomplished by EMN and EMP files. The EMN file is related to the board and the EMP file is the library list of the components on the board. These files can generate a 3D view of the PCB Assembly. IDF files default to the following extensions: *.emn - neutral file of the board outline and component placement and *.emp - profile file that contains component outlines.
PWA = Printed Wiring Assemblies. Excerpts from "Intermediate Data Format Specification, Version 3.0": Structure of the Intermediate Data Format - The Intermediate Data Format consists of three files: the Board File, the Library File and the Panel File.
The Board File: It contains a description of a single PWA, including the board shape, layout restrictions and component placement.
The Library File: It contains descriptions of components used by one or more PWAs.
The Panel File: It contains a description of a manufacturing panel including the panel shape, layout restrictions and the placement of boards and components on the panel.
The Panel File is an optional file, similar to the Board File, that contains the physical description of a manufacturing step-and-repeat panel and the locations of boards and components on that panel. The Panel File references one or more PWAs described in separate Board Files. Any component placed on the panel itself is referenced in a Library File.
The Gerber file
It is a connector and bridge between designers, engineers and PCB manufacturers. It needs to go through every manufacturing process and the factory can clearly define the customer's needs. According to UCAMCO (the company that currently owns the rights to Gerber File format): "Gerber file format" is a standard for PCB design data storage or transfer. Gerber file describes and communicates the constituents of a PCB image like the number of copper layers, solder masks and many others such attributes. Gerber files also act as input files to PCB printing devices like photo-plotters and Automated Optical Inspection (AOI) machines to print or compare circuit board images for different gadgets. Gerber files may also include metadata (data about other constituting data within a file) like solder mask, legend/silk and number of copper layers among other relevant printing information.
Following files comprise the full list of GERBER files which are usually zipped and shared to thermal simulation engineer or PCB Manufacturer.
|Gerber File Type||Extension|
|Top side (copper) Layer||.GTL|
|Bottom side (copper) Layer||.GBL|
|Top Paste Mask||.GTP|
|Bottom Paste Mask||.GBP|
|Top Solder Mask||.GTS|
|Bottom Solder Mask||.GBS|
|Internal Plane Layer 1, 2 ... 16||.GP1, .GP2 ... .GP16|
These softwares are meant for electronics industry mainly and hence contains many built-in objects to expedite the simulation process. They can be summarized as follows:
|Melting point, TMP||As per temperature control||Selection of material will depend on temperature to be maintained|
|Specific heat capacity, Cp||High||Energy storage capacity ∝ Cp. Higher the Cp, lesser the mass required to store a given amount of energy.|
|Density, ρ||High||Energy storage capacity ∝ ρ and the volume required is also less as m = ρ * V|
|Thermal Conductivity, k||High for energy storage purpose||Low value is required for insulation where heat is to be maintained near the source itself|
|Coefficient of volume expansion, γ||Low||This governs flexibility or void space required in the storage container|
|Chemical compatibility||Non-corrosive||Should not react with the container and other materials in case of leaks|
|Thermal cycling (heating-cooling) stability||No degradation||The micro-structure and material properties should not degrade with heating-cooling cycles|
QC = -[S.i.TC − 0.5 × i2R − k.×G×(TH − TC)], negative sign is for heat flow into the device.
QC = -[S.i.TC - 0.5 × i2ρ/G − k×G×(TH − TC)]
Similarly:QH = [S.i.TH + 0.5 × i2R − k.×G×(TH − TC)]
QC = [S.i.TH + 0.5 × i2ρ/G − k×G×(TH − TC)]
Orthotropic conductivity based on lumped block assumptions. 10% Copper is a reasonable guess. In case one needs to use "Locally Varying Orthotropic" thermal conductivity, the detail layout of traces and FR4 layers need to be modelled.
A bit more detailed calculation of thermal conductivity is layer-by-layer estimation also known as "Discrete Layer Stack-up". For each layer:
kLAYER_i = kCu × ACu / APCB + kFRP × AFRP / APCB
A detailed calculation of effective thermal conductivities in X-, Y- and Z-directions can be estimated by spliting the PCB in smaller segements and using smaller patches as described below. This method is useful for capturing conduction paths near heat generating components and heat sinks.
#------------------------------------------------------------------------------ #The comment character is the pound sign (#). A comment must be a separate line #(record) and the comment character must be in column 1. Comments should be #located between, but not within sections of the IDF files. #------------------------------------------------------------------------------ .HEADER BOARD_FILE 3.0 "Sample File Generator" 2020/07/01.16:02:44 1 sample_board THOU .END_HEADER #Unit MM or THOU = milli-inch #------------------------------------------------------------------------------ #Section keyord: .BOARD_OUTLINE or .PANEL_OUTLINE #MCAD - Outline is owned by the Mechanical system and should not be modified in #the Electrical system #ECAD - Outline is owned by the Electrical system and should not be modified in #the Mechanical system #UNOWNED - Outline can be modified in either system #62.0 is thickness in milli-inch #------------------------------------------------------------------------------ .BOARD_OUTLINE MCAD 62.0 0 5030.5 -120.0 0.0 0 5187.5 -120.0 0.0 0 5187.5 130.0 0.0 0 5155.0 130.0 0.0 0 5155.0 550.0 -180.0 ... .END_BOARD_OUTLINE #------------------------------------------------------------------------------ .ELECTRICAL EthnetBrd 135792468 THOU 59.0 0 -92.0 63.0 0 0 -92.0 -63.0 0 0 92.0 -63.0 0 0 92.0 63.0 0 0 -92.0 63.0 0 .END_ELECTRICAL #------------------------------------------------------------------------------ EthnetBrd 135792468 E7 20.5 32.5 0.0 90.0 BOTTOM PLACED
ICEPAK is a GUI for pre- and post-processing. It uses FLUENT as solver and in this process many files get created. Following is a list of files and its owner (ICEPAK or FLUENT?).
|File Type||Created by||Used by||Suffix / Filename||Remark|
|Mesh input||ICEPAK||mesher||grid_input||Inputs for the mesh generator.|
|Mesh output||mesher||ICEPAK||grid_output||Output from the mesh generator that is the mesh file|
|Case||ICEPAK||FLUENT||.cas||Contains all the information that is needed by ICEPAK to run the solver|
|Data||FLUENT||FLUENT||.dat and .fdat||Files when it has finished calculating: *.dat and *.fdat. These data files can be used to restart the solver|
|Residual||FLUENT||ICEPAK||.res||Information about convergence monitors: Solve → Solution monitor or select Convergence plot in Post menu|
|Script||ICEPAK||ICEPAK||.SCRIPT or _sc.bat||Runs the solver executable and can also be used to run the solver in batch mode.|
|Solver input||ICEPAK||FLUENT||.uns_in||The solver input file (projectname.uns_in) is read by the solver to start the calculation.|
|Solver output||FLUENT||–||.uns_out||Information from solver that is displayed on screen during calculation - this file is written only on Linux systems|
|Diagnostic||ICEPAK||–||.diag||Contains information about correspondence between object names in model file and object names in case file|
|Optimization||ICEPAK||optimizer||.log, .dat, .tab, .post, .rpt||Optimization of field variables|
|Postprocessing||FLUENT||ICEPAK||.resd||Used by ICEPAK for post-processing. All solutions that exist for the current project are listed by solution ID.|
|Geometry||External||ICEPAK||.igs, .stp||CAD geometry - input to ICEPAK|
Fan swirl: tangential component of flow at exit of a fan.
Grilles and Louvres:
PCB Gerber File Import
PCB Stack Data
PCB Stack-up Data in Detail
Such fins are extruded or machined and needs to be fixed on the heat generating component using adhesive or screws. This creates a thermal contact resistance and needs to be accounted for temperature calculation of the mating surfaces. The parameter ΔT/[Q.A] can be used in fin selection for given heat dissipation and surface area (available space). Lower the number, better the heat sink design.
|BF||Thickness of fins||[mm]||1||2||2||2||5||5|
|LF||Height of fins||[mm]||20||20||10||20||20||10|
|WF||Width of fins [depth perpendicular to screen]||[mm]||250||250||250||250||100||100|
|AF||Cross-section of fins = BF×WF||[mm2]||250||500||500||500||500||500|
|PF||Perimeter of fins = 2[BF+WF]||[mm]||502||504||504||504||210||210|
|kF||Thermal conductivity of fin||[W/m-K]||100||100||100||100||100||100|
|h||Convective Heat Transfer Coefficient||[W/m2-K]||10||10||20||10||10||10|
|RF||Thermal resistance of each fin||[K/W]||10.23||10.05||9.99||10.05||23.94||47.69|
|iF||Number of fins||[nos]||10||10||10||10||10||10|
|RF||Thermal resistance of all fins||[K/W]||1.02||1.01||0.99||1.01||2.39||4.77|
|Q||Heat transfer rate (all fins)||[W]||58.7||59.7||60.1||59.7||25.1||12.6|
|A||Heat transfer surface area||[cm2]||10||10||5||10||4||2|
|ΔT/[A.Q]||Heat transfer rate||[K/W/cm2]||0.102||0.101||0.200||0.101||0.599||2.384|
Following calculations is valid for pin-type and plate-type fins only.
|Select the type of Fin:|
|Thermal conductivity of fin in [W/m-K]:|
|Specify length or height of fin [mm]:|
|Diameter (pin-type) or thickness (plate-type) of fin [mm]:|
|Width of plate-type fin [mm]:|
|Convective HTC on fin surface [W/m2.K]:|
|Reference temperature [°C]:|
|Base temperature [°C]:|
|Base thickness [mm]:|
|Tip convection [W/m2.K]:|
The heat transfer rate of pin-type fin for natural convection in air is tabulated below. Note the impact of L/D ratio on heat transfer rate.
The values for forced convection in air is tabulated below. 'A' is the heat transfer area of the fin and not the cross-section area. The parameter ΔT/[Q.A] can be used in fin selection for given heat dissipation and surface area (available space). For example, for a heat dissipation of 10 [W] using a fin of diameter 20 [mm] and height 100 [mm], the expected increase in temperature of the base of fin is 10 [W] x 62.8 [cm2] x 0.1431 = 89.9 [K].
The content on CFDyna.com is being constantly refined and improvised with on-the-job experience, testing, and training. Examples might be simplified to improve insight into the physics and basic understanding. Linked pages, articles, references, and examples are constantly reviewed to reduce errors, but we cannot warrant full correctness of all content.
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