Applications of CFD tools in PCB, Board-level and Chassis Level Thermal Simulations
Table of Contents: THERMAL CHARACTERIZATION OF IC PACKAGES | MOSFET | The Gerber file | ICEPAK: Basic Solver Setting | Heat Transfers in Fins | Thermo-Electric Cooling | Thermal Simulations in Data Centres | EMN-EMP Files | FPGA | Efficiency and Power Losses in MOSFETS | Joint Electron Device Engineering Council (JEDEC) standards | Heat Generation Rates in Electronic Parts | IDF and IDX: ECAD - EMN/EMP | Thermal Resistances
There are vast range of applications of thermal simulations in electronics industry dealing with Printed Circuit Board (PCB), IC Chips, Bipolar junction transistor (BJT), Diodes, MOSFET, FPGA, Power Transistors, Bipolar and Darlington Transistors, IGBT, Capacitors, Power Supply, Power Switches, Voltage Regulators, Controllers, Inductors, Solid State Relays, Bulk Acoustic Wave (BAW) Oscillator, Ultra-Low Jiter Oscillator, Flash PROM, Flash Mux, DDR4 SDRAM, DDR Clock Buffer, Digital Step Attenuator, Digital Isolator, Power Sequencer, Phase Locked Loop, Transceiver chip, Control relays, Op-Amp, Analog Multiplier, Silicon-Controlled Rectifiers (SCRs) ... In addition to board and chassis level simulation, thermal management of data centres include specialized cooling methods like heat sinks, TEC (Thermo-Electric Cooling), heat pipes, PCM (Phase Change Material), heat spreaders are also presented in this page. A thermal network model for MOSFET-on-PCB is shown below. The applications include Synchronous Step Down Switcher, Synchronous buck converter, Inverting Buffers / Drivers, DC/DC Controllers, Inverting Schmitt Triggers...
The thermal network is a reasonably accurance and extermely fast approach to evaluate casing temperature of heat generating devices. TNsolver is a free open-source code written in GNU Octave to solver such thermal networks. For application of Machine Leaning in predicting thermal aspects of such devices, refer the article "Approximating the Steady-State Temperature of 3D Electronic Systems with Convolutional Neural Networks" by Monika Stipsitz and Hèlios Sanchis-Alepuz.
Equivalence of Radiative Heat Transfer Rate at Low Temperature and Small Temperature Differences
Convective heat transfer rate: qCNV'' = h x [T - TREF].Radiative heat flux rate: qRAD'' = ε x σ x [TW14 - TW24] = ε x σ x [TW1 - TW2] x [TW1 + TW2] x [TW12 + TW22]
Comparing the two equations: hRAD ≡ ε x σ x [TW1 + TW2] x [TW12 + TW22]
For ε = 1.0, TW1 = 100 [°C] and TW2 = 40 [°C], hRAD = 9.23 [W/m2.K]For ε = 1.0, TW1 = 80 [°C] and TW2 = 40 [°C], hRAD = 8.41 [W/m2.K]
For ε = 1.0, TW1 = 60 [°C] and TW2 = 50 [°C], hRAD = 8.01 [W/m2.K]
As you can see, the convective heat transfer coefficient in natural convection with air ranges between 5 to 15 [W/m2.K]. Hence, the contribution of radiation in natural convection cases (such as electronic cooling) is approximatly equal to the convective heat transfer rate. In other words, convection and radiation contribute almost equal in natural convection heat transfer cases dealing with low temperature differences.
In general, the heat dissipation through the bodies of devices become difficult when the volume density of heat generation rate exceeds 108 [W/m3]. Such devices are often connected to the PCB with thermal vias having thickness ~ 0.5 [mm].
Four ways PCB are modeled in ICEPAK
"PCB is developed to mechanically support and electrically connect electronic components through conductive tracks and pads. Components are typically soldered onto the PCB to be mechanically and electrically connected to it. Many active (for example, operational amplifiers and batteries) and passive components (such as inductors, resistors, and capacitors) are mounted on the PCBs."Inputs Required for Thermal Simulations:
The inputs from PCB Design (Hardware Team) to the thermal simulation team should be provided in the format described below.
S. No. | Reference Designator | Qty | Vendor Part Number | Output Power [W] | Efficiency [%] | Heat Generation Rate [W] | Mounting type on PCB |
01 | U1 | 1 | LTM123 | 5.0 | 75% | 1.25 | Vias and pin with airgap |
02 | U2 | 5 | MJ1201 | 0.2 | 80% | 0.04 | Full Contact |
... | ... | ... | ... | ... | ... | ... | TIM |
... | ... | ... | ... | ... | ... | ... | Soldered Pins with airgap |
Power Budget of the PCB Board: Energy balance helps in checking for correctness of the inputs - "worst-case estimates" sometimes have too much margin (extra heat generation rate) to keep the temperatures low. | |||||||
Total input power to the PCB Board [W]: | 20.0 | ||||||
Total ouput power to the PCB Board [W]: | 16.0 | ||||||
Heat generation in the copper traces inside PCB Board [W]: | 0.50 |
For linear regulators, total current is sum of all currents, regardless of voltage. For switchers, efficiency is required to calculate required current at given voltage. Power distribution network (PDN) ensures stable power supply to all electronic components. PDN consists of traces, vias, planes, Voltage Regulators, and decoupling capacitors. PDN distributes power from the primary source throughout the PCB board to ensure voltage supply to various components. A good source to understand basics of PCB design is "tessolve.com/blogs/power-distribution-network-in-pcb-design-ensuring-stable-power-delivery".
Heat Generation and Heat Transfer Path
The units of power and heat, both are [W] and it creates confusion while interpreting the information among power-electronics or hardware designers and mechanical thermal engineers. The heat generation rate of a device is difference between power input and power output and it is important to note that power delivered by a device to a load is not power dissipated in the device as heat. When no specific efficiency curves are available in a data sheet for the application, an assumption of the efficiency is to be considered to calculate the input power. Typically, this value can range between 70% to 90%. in case CDR (Direct Current Resistance) is known from the data sheet, it is easy to calculate heat generation rate in the device. For many devices, the power dissipation consists of two basic components - the unloaded power dissipation inherent to the device and the load power dissipation which is a function of the device loading. For example, the loading of a logic device can significantly effect the power dissipation. Most of the logic loads are capacitive, leading to more of dynamic power dissipation.The effect of radiation heat transfer is very important in natural convection, as it can contribute to approximately 25% of the total heat dissipation. Unless the components are facing hotter surface nearby such as enclosure, the radiative heat transfer must be accounted for.
Many devices are mounted to the PCB though the connector pins and the case is not in full contact with the PCB. This mounting arrangement must be taken into account to model the heat transfer path from case to the PCB. One option is to compare the contact area of the pins and PCB with that of the case and PCB and apply appropriate contact resistance.Die: It designates the piece of semiconductor on which all the active circuits lie. Dies are made of Silicon (110 – 150 W/m.K) or Gallium Arsenide (GaAs, 45 – 60 W/m.K) is used in special applications such as microwaves. The circuitry is present within a thin layer on one side only, known as active surface. The concept of "junction temperature" applies to the top surface of the die. The heat flux in the die and die-attach is very high, the junction temperature is very sensitive to the thermal conductivity and the thickness of the die and die-attach.
The Die is often attached to the substrate or the die pad by an adhesive known as the "die attach" which is made of an epoxy based compound having thickness 0.025 - 0.050 [mm] and thermal conductivity in the range 1 - 2 [W/m.K]. The semiconductor material of a die has a conductivity approaching that of a metal. If the active layer is assumed to generate constant power per unit area (an assumption that may not always be valid), the die will be practically isothermal. In practice, applications exist for which the heat flux varies significantly across the die, in which case a temperature gradient may exist on its active surface. For most packages, the thermal resistance offered by the die is small in comparison with that offered by the rest of the package. Referecnce: FloTHERM Pack User's Guide
Due to low thickness of the "die attach", it causes very little heat spreading. At the same time, it offers significant thermal resistance in out-of- the-plane direction due to its poor thermal conductivity value. Si is very widely used because of its cheap price, easiness in processing and fairly high thermal conductivity. SiC is an alternative material [though very costly] that has high thermal conductivity of 370 [W/m-K].
Die Pad or Die Flag: The Die is placed in insulated boxed often plastic packages, on a thin metal plate (made of copper and larger than the die) known as the die flag or die pad. It helps both in the manufacturing and thermal (heat dissipation) function. The metallic die flag acts as an effective heat spreader due to very high thermal conductivity of copper which can reduce the thermal resistance of a package by up to 15%.
Bond wires, made of Gold or Aluminum having diameter of the order of 0.025 [mm], are characteristics of wire-bonded packages. The number of bond wires in an IC package are of same order as the number of external leads/pins. Excerpts from "FloTHERM Pack User's Guide": In most ceramic packages, a negligible portion of the heat from the Die flows to the substrate through the bond wires. However, in plastic packages this may not be the case. Bond wires play a significant role in the heat transfer within peripheral leaded packages such as the PQFP. In area-array plastic packages such as the PBGA, bond wires can be important, especially for a 2-layer substrate.
Encapsulant: Also known as 'Overmold', it is an epoxy based compound with a thermal conductivity 0.6 - 0.7 [W/m.K].
Reference: FloTHERM PACK User Guide
CBGA = Ceramic Ball Grid Array, PBGA = Plastic Ball Grid Array, TBGA: Tape Ball Grid Array, CPGA: Ceramic Pin Grid Array Thermal conductivities: Alumina - 21 [W/m-K], Kovar - 17 [W/m-K], Typical encapsulant and elastomer material - 0.4 ~ 0.6 [W/m-K], Polyimide: 0.2 [W/m-K], 37Pb/63Sn solder: 50 [W/m-K]Two-resistor model is a relatively simple model achieved by dividing a package vertically at the junction and is good for single function devices. However, this model has the least precise as compared to multi-resistor network and detailed thermal models. This model (like any thermal resistor model) does not support "Transient Analyses". The methods of thermal resistance measurement are described for θJB in JEDEC Standard JESD51-8 and for θJC in JESD51-14.
In general, thermal resistance Θ or RTH = ΔT / P where P is power dissipation from the chip package in [W] and ΔT = TJ - TA.
Sample from datasheet of a DD-DC Step-down Power Supply from Linear Technology: TJ is the junction temperature and TA is the ambient temperature. In other words, the thermal resistance of an IC package is defined as the amount of heat generated or a rise in temperature when 1 [W] of power is dissipated in the IC. E.g. if an IC package generate 0.50 [W] with Junction-to-Ambient thermal resistance of 100 [K/W], the temperature of junction will rise by 0.5 [W] × 100 [K/W] = 50 [K] over the ambient. The construction of IC packages decides the thermal resistances: few types are Dual Inline Packages (DIP), Ceramic through-hole package, Plastic through-hole package, Plastic leaded chip carrier (PLCC), Quad Flat Package (QFP), Plastic dual construction surface mounte package, Thin small outline package (TSOP)...The standard test conditions are specified by Joint Electron Device Engineering Council (JEDEC) such as JESD15-3: Two-Resistor Compact Thermal Model Guideline, JESD51: Methodology for the Thermal Measurement of Component Packages (Single Semiconductor Device), JESD51-9 "Test Boards for Area Array Surface Mount Package Thermal Measurements" and JESD51-12: Guidelines for Reporting and Using Package Thermal Information.
As described in webinar "Understanding Datasheet Thermal Parameters and IC Junction Temperatures" by Monolithic Power Systems - ΘJA is valid only for its defined PCB and it is not a constant which can be used on all PCBs. ΘJA allows comparison of different packages on a common PCB.
As per datasheet for LTM8023: "θJA is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclosure. This environment is sometimes referred to as still air although natural convection causes the air to move. This value is determined with the part mounted to a JESD 51-9 defined test board, which does not reflect an actual application or viable operating condition."Another use of RJA or ΘJA, is to calculate parameter called derating factor when the power dissipation values are unspecified in the datasheet. Using the formula TJ = TA + P × ΘJA, the permissible heat generation rate can be estimate for various ambient temperatures say between 25 [°C] to 75 [°C].
As described in datasheet for LTM8023: "θJCbottom is the junction-to-board thermal resistance with all of the component power dissipation flowing through the bottom of the package. In the typical μModule regulator, the bulk of the heat flows out the bottom of the package, but there is always heat flow out into the ambient environment. As a result, this thermal resistance value may be useful for comparing packages but the test conditions don’t generally match the user’s application. θJCtop is determined with nearly all of the component power dissipation flowing through the top of the package. As the electrical connections of the typical μModule regulator are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. As in the case of θJCbottom, this value may be useful for comparing packages but the test conditions don’t generally match the user’s application."
As described in datasheet for LTM8023: "θJB is the junction-to-board thermal resistance where almost all of the heat flows through the bottom of the μModule regulator and into the board, and is really the sum of the θJCbottom and the thermal resistance of the bottom of the part through the solder joints and through a portion of the board. The board temperature is measured a specified distance from the package, using a two sided, two layer board. This board is described in JESD 51-9."
The Thermal Resistance is calculated in a condition where nearly all of the component power dissipation flows through either the top or the bottom of the package. In calculating the Thermal Characterization Parameter, power is the total power dissipation in the chip which can flow out of the chip through any thermal path, not just from the top or the bottom of the package.
The heat transfer path and various thermal resistance as described above are explained in the schematic from Aavid Thermalloy Inc which is shown below. From the definitions and explanation above, it can be deduced that "Junction-to-ambient thermal resistance" should always be higher than "Junction-to-case thermal resistance" and "Junction-to-board thermal resistance". However, this is not the case: refer the screenshot from device LMK6X, Texas Instruments' Bulk-Acoustic Wave (BAW)Example Calculation - 1: A transistor with power rating of 10 [W] and internal thermal resistance of 1.5 [K/W] has a case temperature of 60 [°C]. What is the actual value of junction temperature?
Here:Example Calculation - 2: A chip with 5 [W] rating has a maximum junction temperature of 120 [°C] and an internal resistance of 0.5 [K/W] at an ambient of 40 [°C] with aluminium oxide wafers. What is the maximum permissible thermal resistance of the heatsink?
Excerpts from "Semiconductor and IC Package Thermal Metrics" by Texas Instruments: RΘJA is a variable function of not just the package, but of many other system level characteristics such as the design and layout of the PCB on which the part is mounted. In effect, the test board is a heat sink that is soldered to the leads of the device. Changing the design or configuration of the test board changes the efficiency of the heat sink and therefore the measured RθJA. In fact, in still-air JEDEC-defined RΘJA measurements, almost 70 ~ 95% of the power generated by the chip is dissipated from the test board, not from the surfaces of the package. Because a system board rarely approximates the test coupon used to determine RΘJA, application of ΘJA using
[TJ = TA + RΘJA × P]
results in extremely erroneous values.The document further elaborates: "In light of the fact that RΘJA is not a characteristic of the package by itself but of the package, PCB and other environmental factors, it is best used as a comparison of package thermal performance between different companies. For example, if TI reports an RΘJA of 40 [°C/W] or 40 [K/W] for a package compared to a competitor's value of 45 [K/W], the TI part will likely run 10% cooler in an application than the competitor's part." As a "margin of safety", the permissible limit of junction temperature should be reduced by 20-30 [°C] from the value specified by the manufacturers.
Excerpts from "Thermal Design Basics" by Analog Devices: In ICs, one temperature reference point is always the device junction, taken to mean the hottest spot inside the chip operating within a given package. The other relevant reference point will be either TC - the case of the device, or TA - that of the surrounding air. This then leads in turn to the above mentioned individual thermal resistances ΘJC and ΘJA. Taking the most simple case first, ΘJA is the thermal resistance of a given device measured between its junction and the ambient air. This thermal resistance is most often used with small, relatively low power ICs such as op-amps, which often dissipate 1 [W] or less. Generally, ΘJA figures typical of op-amps and other small devices are on the order of 90-100 [°C/W] for a plastic 8-pin DIP package, as well as the better SOIC packages.
Excerpts from a datasheet: "The LTM8023MP is guaranteed to meet specifications over the full –55 °C to 125 °C temperature range. Note that the maximum internal temperature is determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors."
S. No. | Field Parameter | JESD51 | Application / Thermal Simulation | Remark |
01 | PCB | 1.6 [mm] thick, 4.0 x 4.5[in], 2-4 layers | 6-15 layers, high thermal conductivity | 1s0p, 2s2p (s: signal layer, p: power layer) |
02 | Enclosure | 30 x 30 x 30 [cc] | Smaller or bigger | Enclosure shape and size irregular |
03 | Board position | Horizontal | Can be horizontal, vertical or inclined | Minimize convection to air |
04 | Package mounting | Up | Up, Down, Back-to-back | Package can be mounted on both sides of PCB |
05 | Measurement point | Centre of top case | Maximum in component volume | Maximum in volume is taken to make a safer estimate |
06 | Heat dissipation | Top face of package case only | Top face, side faces and through pins to PCB: volumetric heat source | Refer the image below for test set-up |
07 | Calculation of RθJC | (TJ - TC) / P | TJ = TC + RθJC x PCASE where PCASE = heat transfer through case only | RθJC remains constant |
08 | Recommended method | RθJC is for 'theoretical' comparison of two designs | Use ΨJT which is better representation of real world: TJ = TC + ΨJT x P | RθJC measurement 'forces' all heat to casing |
FPGA: Field Programmable Gate Array
As per Intel documents for Agilex 7 FPGA: "Thermal parameters do not include the traditional junction-to-case thermal resistance (θJC) and junction-to-board thermal resistance (θJB) values, due to its multi-chip package construction." The system-level thermal analysis of this product requires the use of its compact thermal model (CTM) in a computational fluid dynamic (CFD) tool. The CTMs are simplified mechanical models of the packages with modified thermal properties so they can predict an accurate case temperature with uniform power distribution for each die. The results of the CFD analysis are valid only to evaluate the TCASE which is temperature at the top center of the IHS - (Integrated Heat Spreader, case of an FPGA) of the package. TDP: Thermal Design Power, the power dissipated in a die that is used for thermal analysis purposes.Virtex UltraScale and Virtex UltraScale+ are, ASIC-class architecture, FPGA product family from AMD. Excerpts from UltraScale+ Device Packaging and Pinouts Product Specification User Guide (UG575): "Unlike features in an ASIC or a microprocessor, the combination of FPGA features used in a user application is not known to the component supplier. Therefore, it remains a challenge for AMD to predict the power requirements of a given FPGA when it leaves the factory. Accurate estimates are obtained when the board design takes shape. For this purpose, AMD offers and supports a suite of integrated device power analysis tools to help users quickly and accurately estimate their design power requirements." The document further contains thermal resistance data with following notes: "The data includes junction-to-ambient in still air, junction-to-case, and junction-to-board data based on standard JEDEC four-layer measurements. The data in Table 10-1 is for device/package comparison purposes only. Attempts to recreate this data are only valid using the transient 2-phase measurement techniques outlined in JESD51-14. This data is not to be used in place of thermal simulation. Instead, refer to the thermal models provided for each device." In the chapter "Thermal Management Strategy", the document elaborates: "These resistances are measured using a prescribed JEDEC standard that might not necessarily reflect your actual board conditions and environment. The quoted θJA and θJC numbers are environmentally dependent, and JEDEC has traditionally recommended that these be used with that awareness."
Thermal interface material is needed because even the largest heat sink and fan cannot effectively cool an UltraScale or UltraScale+ device unless there is good physical contact between the base of the heat sink and the top of the UltraScale or UltraScale+ device. The surfaces of both the heat sink and the UltraScale or UltraScale+ device silicon are not absolutely smooth. This surface roughness is observed when examined at a microscopic level. Because surface roughness reduces the effective contact area, attaching a heat sink without a thermal interface material is not sufficient due to inadequate surface contact.
AMD advises against direct use of the θJC parameters to determine the thermal performance of the device in your application. The calculation of these parameters are done in accordance with the JEDEC standard JESD51 where system parameters differ greatly from most applications. Instead, run thermal simulations of the system in worst-case environmental conditions using Delphi thermal models, which more accurately represent the device thermal performance under all boundary conditions.
The thermal validation of FPGA thus needs to be performed using Compat Thermal Models (CTM) such as DELPHI model shown below (reference: Delphi Compact Thermal Model Guideline).It is important to keep in mind that the availability of the DELPHI compact model does not eliminate the need for understanding the application in which the package is to be used. In other words, it is the user’s responsibility to take into account the environment surrounding the package.Reference: MOSFET power losses and how they affect power-supply efficiency - by By George Lakkas, Product Marketing Manager, Power Management
MOSFETs have a finite switching time, therefore switching losses come from the dynamic voltages and currents the MOSFETs must handle during the time it takes to turn on or off. MOSFET switching losses are a function of load current and the switching frequency of power supply. There are 3 types of losses: conduction losses, switching losses and static (quiescent) losses.
Most of the power is in the MOSFET gate driver. Gatedrive losses are frequency dependent and are also a function of the gate capacitance of the MOSFETs. When turning the MOSFET on and off, the higher the switching frequency, the higher the gate-drive losses. This is another reason why efficiency goes down as the switching frequency goes up.
Reference: AN90003 - LFPAK MOSFET thermal design guide
The list of Joint Electron Device Engineering Council (JEDEC) standards related to thermal characterization of IC chips are:
Heat Generation Rates in Electronic Parts
The DSOP Advance package has a top source side cooling plate in addition to the bottom drain side plate as shown in Figure 2. These cooling plates contribute in reducing the thermal resistance (Rth).
At thermal equilibrium, the maximum power dissipation PDMAX of a power MOSFET can be expressed in terms of the ambient temperature TA, the maximum channel temperature TCHMAX of the MOSFET and the channel-to-ambient thermal resistance RTHCH-A
Component | Material | Thermal Conductivity [W/m-K] | Density | Specific Heat Capacity [J/kg-K] |
Capacitor | Aluminium Oxide | 30 | 3890 | 880 |
MOSFET | Silicon | 80 ~ 150* | 2390 | 712 |
Thermal Grease | SiC | 0.42 | 2500 | 750 |
A PCB trace is a thin line of conducting copper placed on a non-conductive base material usually called FR4 that carries the signal and power to the whole circuit. A copper trace has a specific width called trace width, and a particular thickness. The thickness of PCB is specified in ounce/ft2 = 28.35 gm/ft2 = 0.3052 [kg/m2] = 0.3042/8900 = 3.43 x 10-5 [m] = 0.0343 [mm]. For typical PCBs, the most common copper thickness is specified as 35 [μm] which is equivalent to 1.0 [oz/ft2]. With electrical resistivity of 1.72 x 10-8 [Ω.m] at 25 [°C] for copper, the electrical resistance per inch width per meter length of copper trace is 0.02 [Ω]. The electrical resistance per inch width per inch length of copper trace would be 0.50 [mΩ]. The resistance value shall increase in direct proportion of the length and inverse proportion of the width and/or thickness (mm or oz/ft2).
For example, electrical resistance per inch width per inch length of copper trace having thickness of 2.0 [oz/ft2] would be 0.50 / 2 = 0.25 [mΩ]. Electrical resistance per 0.1 inch width per inch length of copper trace having thickness of 2.0 [oz/ft2] would be 0.50 / 2 / 0.1 = 2.5 [mΩ]. Electrical resistance per 0.1 inch width per meter length of copper trace having thickness of 1.0 [oz/ft2] would be 0.50 * 39.37 / 0.1 = 0.197 [Ω].
With temperature coefficient of electrical resistance 0.0039 [1/K], electrical resistance per 0.1 inch width per meter length of copper trace having thickness of 1.0 [oz/ft2] at 100 [°C] would be 0.197 x [1 + 0.0039 x 75] = 0.255 [Ω]
Trace Heating: In the electrical wires the cooling rate initially increase with thickness of insulation, reaches a peak and then starts decreasing. Similarly, the temperature of traces are dependent on the board thickness, traces on top of a thin board get hotter than one on a thicker board. This is because a thicker board has higher cross-section for the heat to conduct through. Beyond a thickness of board, there is more material under the trace than the trace can efficiently utilize - the path to surface on which convection occurs gets longer - and hence there is no improvement in temperature or in fact the temperature of traces may increase further. PCB trace temperatures are very sensitive to thermal conductivity though the in-plane thermal conductivity has higher influence than through-plane value.
There are many programs used to generate design of electronic items such as PCB and chips. Cadence, EasyEDA, Eagle, Altium Designer, Siemens Expedition Enterprise to name few. However, there is a need to have interface between ECAD and MCAD. This is accomplished by EMN and EMP files. The EMN file is related to the board and the EMP file is the library list of the components on the board. These files can generate a 3D view of the PCB Assembly. IDF files default to the following extensions: *.emn - neutral file of the board outline and component placement and *.emp - profile file that contains component outlines.. A sample EMN file commented with explanation of the information can be found here.
While reading .EMN file in other MCAD programs such as ANSYS Discovery or Creo, the model tree may contain only the names of size designators and reference designator or actual part number may be missing. A reference designators are combination of letters and numbers assigned to PCB components, such as resistors, capacitors, and other electronic elements which provide a standardized way to identify and reference components on the board.This may only give a good representation of the board but one cannot do further processing such as assigning heat generation rates, material properties... To get Mechanical Models with different part names, ECAD Design Software should be set to output package types as the ecad_name and (a) either an internal corporate part number or (b) a vendor part number as the ecad_alt_name. Do not set up ECAD IDF output to use identical ecad and ecad_alt names. AR = Amplifier, C = Capacitor, D = Diode, F = Fuse, FB = Ferrite Bead, J = Connector / Jack Connector, K = Relay, L = Inductor, LED = Light Emitting Diode, M = Motor, P = Plug, PS = Power supply, Q = Transistor, R = Resistor, S = Switch, T or XMER = Transformer, TP = Test Point, TR = Transistor or transducer, U = Integrated Circuit. For example, R1 might refer to the first resistor on the board, C2 could be the second capacitor, and U3 might represent the third integrated circuit. More information at resources.altium.com/p/altium-designer-helps-you-track-reference-designators-your-pcb such as the image below.Reference: simplifiedsolutionsinc.com/images/Steps-to-create-3D-PCBs-in-ProE.pdf: In Pro/E (predecessor to Creo), there was an option to create an ecad_hint.map file which linked components in CAD Tool to 3D Pro/Engineer Model. When an IDF (emn) File is imported into Pro/Engineer, Pro/E cross-referenced the ecad_name and ecad_alt_name from the emn file against the ecad_hint.map. If a match was found, Pro/Engineer replaced "on the fly" geometry with a real 3D Pro/Engineer part or assembly. More information can be found at support.ptc.com/.../Map_File_Standard_Conventions.html
Sample ecad_hint.map file. Each section begins with the purpose, followed by '->'. Each section ends with 'end'. # is the comment character. Wildcard (*) is valid for 'all'. Object and value fields are separated by a space, spaces are permitted in value strings if the string is surrounded by quotation marks.
mcad_in_ignore -> ecad_name "resistor" ecad_alt_name "res_5" ecad_type "part" ref_des "*" endAs per Alitum documentation under "Mechanical Data Import-Export Support": "In the STEP file, each component is identified by its designator. If the MCAD designer needs to import multiple boards into a single MCAD file there is likely to be designator clashes, to avoid this include a Component Suffix."
PWA = Printed Wiring Assemblies. Excerpts from "Intermediate Data Format Specification, Version 3.0": Structure of the Intermediate Data Format - The Intermediate Data Format consists of three files: the Board File, the Library File and the Panel File.
The Board File: It contains a description of a single PWA, including the board shape, layout restrictions and component placement.
The Library File: It contains descriptions of components used by one or more PWAs. *.emp is the extension of the library file.
The Panel File: It contains a description of a manufacturing panel including the panel shape, layout restrictions and the placement of boards and components on the panel.
The Panel File is an optional file, similar to the Board File, that contains the physical description of a manufacturing step-and-repeat panel and the locations of boards and components on that panel. The Panel File references one or more PWAs described in separate Board Files. Any component placed on the panel itself is referenced in a Library File.
Note: "The comment character is the pound or hash sign (#). A comment must be a separate line (record) and the comment character must be in column 1. Comments should be located between, but not within sections of the IDF files." The Header section must be the first section in the file, the second section must be the Outline section, and the last section must be the Placement section. All other sections may be in any order. Exporting IDF files in Atlium wil1 generate two files - one containing information about the physical size and shape of PCB and positions of components, the other containing information about each component including name, size, and shape. These are typically referred to as the board and library files, respectively. Different CAD packages use different file extensions for the board and library files. The board file and library file extensions of generated files have following pairs: .brd and -pro, .brd and .lib, emn and emp, . bdf and.ldf, .idb and .idl, .idf and .lib. Note that EMP is for describing parts that equip the board. Thus, for a PCB (without parts on it), no EMP file will be generated.The Gerber file
It is a connector and bridge between designers, engineers and PCB manufacturers. It needs to go through every manufacturing process and the factory can clearly define the customer's needs. According to UCAMCO (the company that currently owns the rights to Gerber File format): "Gerber file format" is a standard for PCB design data storage or transfer. Gerber file describes and communicates the constituents of a PCB image like the number of copper layers, solder masks and many others such attributes. Gerber files also act as input files to PCB printing devices like photo-plotters and Automated Optical Inspection (AOI) machines to print or compare circuit board images for different gadgets. Gerber files may also include metadata (data about other constituting data within a file) like solder mask, legend/silk and number of copper layers among other relevant printing information.
Following files comprise the full list of GERBER files which are usually zipped and shared to thermal simulation engineer or PCB Manufacturer.
Gerber File Type | Extension |
Top side (copper) Layer | .GTL |
Bottom side (copper) Layer | .GBL |
Top Overlay | .GTO |
Bottom Overlay | .GBO |
Top Paste Mask | .GTP |
Bottom Paste Mask | .GBP |
Top Solder Mask | .GTS |
Bottom Solder Mask | .GBS |
Keep-Out Layer | .GKO |
Drill Drawing | .GD1 |
Drill Guide | .GG1 |
Internal Plane Layer 1, 2 ... 16 | .GP1, .GP2 ... .GP16 |
"Electronic Schematics: Schematics communicate specific information about how electronics in a design should be connected to each other. Components are labeled with their electrical characteristics, such as capacitance or resistance, with the complete circuit being illustrated across the PCB. The schematic is an organized view of the electrical circuit and provides necessary information for manufacturing."
#------------------------------------------------------------------------------ #The comment character is the pound sign (#). A comment must be a separate line #(record) and the comment character must be in column 1. Comments should be #located between, but not within sections of the IDF files. #------------------------------------------------------------------------------ .HEADER BOARD_FILE 3.0 "Sample File Generator" 2020/07/01.16:02:44 1 sample_board THOU .END_HEADER #Unit MM or THOU = milli-inch #------------------------------------------------------------------------------ #Section keyord: .BOARD_OUTLINE or .PANEL_OUTLINE #MCAD - Outline is owned by the Mechanical system and should not be modified in #the Electrical system #ECAD - Outline is owned by the Electrical system and should not be modified in #the Mechanical system #UNOWNED - Outline can be modified in either system #62.0 is thickness in milli-inch #------------------------------------------------------------------------------ .BOARD_OUTLINE MCAD 62.0 0 5030.5 -120.0 0.0 0 5187.5 -120.0 0.0 0 5187.5 130.0 0.0 0 5155.0 130.0 0.0 0 5155.0 550.0 -180.0 ... .END_BOARD_OUTLINE #------------------------------------------------------------------------------ .ELECTRICAL EthnetBrd 135792468 THOU 59.0 0 -92.0 63.0 0 0 -92.0 -63.0 0 0 92.0 -63.0 0 0 92.0 63.0 0 0 -92.0 63.0 0 .END_ELECTRICAL #------------------------------------------------------------------------------ EthnetBrd 135792468 E7 20.5 32.5 0.0 90.0 BOTTOM PLACED
These softwares are meant for electronics industry mainly and hence contains many built-in objects to expedite the simulation process. They can be summarized as follows:
Characterisitcs | Desired value | Remark |
Melting point, TMP | As per temperature control | Selection of material will depend on temperature to be maintained |
Specific heat capacity, Cp | High | Energy storage capacity ∝ Cp. Higher the Cp, lesser the mass required to store a given amount of energy. |
Density, ρ | High | Energy storage capacity ∝ ρ and the volume required is also less as m = ρ * V |
Thermal Conductivity, k | High for energy storage purpose | Low value is required for insulation where heat is to be maintained near the source itself |
Coefficient of volume expansion, γ | Low | This governs flexibility or void space required in the storage container |
Chemical compatibility | Non-corrosive | Should not react with the container and other materials in case of leaks |
Thermal cycling (heating-cooling) stability | No degradation | The micro-structure and material properties should not degrade with heating-cooling cycles |
Field Variables
QC = -[S.i.TC − 0.5 × i2R − k.×G×(TH − TC)], negative sign is for heat flow into the device.
Or
QC = -[S.i.TC - 0.5 × i2ρ/G − k×G×(TH − TC)]
Similarly:
QH = [S.i.TH + 0.5 × i2R − k.×G×(TH − TC)]Or
QC = [S.i.TH + 0.5 × i2ρ/G − k×G×(TH − TC)]
Orthotropic conductivity based on lumped block assumptions. 10% Copper is a reasonable guess. In case one needs to use "Locally Varying Orthotropic" thermal conductivity, the detail layout of traces and FR4 layers need to be modelled.
kLAYER_i = kCu × ACu / APCB + kFRP × AFRP / APCB
A detailed calculation of effective thermal conductivities in X-, Y- and Z-directions can be estimated by spliting the PCB in smaller segements and using smaller patches as described below. This method is useful for capturing conduction paths near heat generating components and heat sinks.
ICEPAK is a GUI for pre- and post-processing. It uses FLUENT as solver and in this process many files get created. Following is a list of files and its owner (ICEPAK or FLUENT?).
File Type | Created by | Used by | Suffix / Filename | Remark |
Model | ICEPAK | ICEPAK | model | |
Problem | ICEPAK | ICEPAK | problem | |
Job | ICEPAK | ICEPAK | job | |
Mesh input | ICEPAK | mesher | grid_input | Inputs for the mesh generator. |
Mesh output | mesher | ICEPAK | grid_output | Output from the mesh generator that is the mesh file |
Case | ICEPAK | FLUENT | .cas | Contains all the information that is needed by ICEPAK to run the solver |
Data | FLUENT | FLUENT | .dat and .fdat | Files when it has finished calculating: *.dat and *.fdat. These data files can be used to restart the solver |
Residual | FLUENT | ICEPAK | .res | Information about convergence monitors: Solve → Solution monitor or select Convergence plot in Post menu |
Script | ICEPAK | ICEPAK | .SCRIPT or _sc.bat | Runs the solver executable and can also be used to run the solver in batch mode. |
Solver input | ICEPAK | FLUENT | .uns_in | The solver input file (projectname.uns_in) is read by the solver to start the calculation. |
Solver output | FLUENT | – | .uns_out | Information from solver that is displayed on screen during calculation - this file is written only on Linux systems |
Diagnostic | ICEPAK | – | .diag | Contains information about correspondence between object names in model file and object names in case file |
Optimization | ICEPAK | optimizer | .log, .dat, .tab, .post, .rpt | Optimization of field variables |
Postprocessing | FLUENT | ICEPAK | .resd | Used by ICEPAK for post-processing. All solutions that exist for the current project are listed by solution ID. |
Log | ICEPAK | ICEPAK | .log | |
Geometry | External | ICEPAK | .igs, .stp | CAD geometry - input to ICEPAK |
Packaged | ICEPAK | ICEPAK | .tzr | Project archive |
Fan swirl: tangential component of flow at exit of a fan.
Heat Sinks:
Grilles and Louvres:
PCB Stack-up Data in Detail
Such fins are extruded or machined and needs to be fixed on the heat generating component using adhesive or screws. This creates a thermal contact resistance and needs to be accounted for temperature calculation of the mating surfaces. The parameter ΔT/[Q.A] can be used in fin selection for given heat dissipation and surface area (available space). Lower the number, better the heat sink design.
BF | Thickness of fins | [mm] | 1 | 2 | 2 | 2 | 5 | 5 |
LF | Height of fins | [mm] | 20 | 20 | 10 | 20 | 20 | 10 |
WF | Width of fins [depth perpendicular to screen] | [mm] | 250 | 250 | 250 | 250 | 100 | 100 |
AF | Cross-section of fins = BF×WF | [mm2] | 250 | 500 | 500 | 500 | 500 | 500 |
PF | Perimeter of fins = 2[BF+WF] | [mm] | 502 | 504 | 504 | 504 | 210 | 210 |
kF | Thermal conductivity of fin | [W/m-K] | 100 | 100 | 100 | 100 | 100 | 100 |
h | Convective Heat Transfer Coefficient | [W/m2-K] | 10 | 10 | 20 | 10 | 10 | 10 |
NF | Fin parameter | [m-1] | 14.17 | 10.04 | 14.20 | 10.04 | 6.48 | 6.48 |
RF | Thermal resistance of each fin | [K/W] | 10.23 | 10.05 | 9.99 | 10.05 | 23.94 | 47.69 |
iF | Number of fins | [nos] | 10 | 10 | 10 | 10 | 10 | 10 |
RF | Thermal resistance of all fins | [K/W] | 1.02 | 1.01 | 0.99 | 1.01 | 2.39 | 4.77 |
ΔT | Temperature potential | [K] | 60 | 60 | 60 | 60 | 60 | 60 |
Q | Heat transfer rate (all fins) | [W] | 58.7 | 59.7 | 60.1 | 59.7 | 25.1 | 12.6 |
A | Heat transfer surface area | [cm2] | 10 | 10 | 5 | 10 | 4 | 2 |
ΔT/[A.Q] | Heat transfer rate | [K/W/cm2] | 0.102 | 0.101 | 0.200 | 0.101 | 0.599 | 2.384 |
Select the type of Fin: | |
Thermal conductivity of fin in [W/m-K]: | |
Specify length or height of fin [mm]: | |
Diameter (pin-type) or thickness (plate-type) of fin [mm]: | |
Width of plate-type fin [mm]: | |
Convective HTC on fin surface [W/m2.K]: | |
Reference temperature [°C]: | |
Base temperature [°C]: | |
Base thickness [mm]: | |
Tip convection [W/m2.K]: | |
The heat transfer rate of pin-type fin for natural convection in air is tabulated below. Note the impact of L/D ratio on heat transfer rate.
L | [mm] | 100.0 | 100.0 | 100.0 | 100.0 | 100.0 | 100.0 | 100.0 |
D | [mm] | 5.0 | 10.0 | 20.0 | 25.0 | 50.0 | 100.0 | 200.0 |
h | [W/m2-K] | 10.0 | 10.0 | 10.0 | 10.0 | 10.0 | 10.0 | 10.0 |
ΔT | [K] | 60.0 | 60.0 | 60.0 | 60.0 | 60.0 | 60.0 | 60.0 |
NF | [m-1] | 8.9 | 6.3 | 4.5 | 4.0 | 2.8 | 2.0 | 1.40 |
A | [cm2] | 15.7 | 31.4 | 62.8 | 78.5 | 157.1 | 314.2 | 628.3 |
Q | [W] | 0.7520 | 1.6680 | 3.5370 | 4.4760 | 9.18 | 18.60 | 37.45 |
ΔT/[A.Q] | [K/W/cm2] | 5.079 | 1.145 | 0.270 | 0.1707 | 0.0416 | 0.0103 | 0.0025 |
The values for forced convection in air is tabulated below. 'A' is the heat transfer area of the fin and not the cross-section area. The parameter ΔT/[Q.A] can be used in fin selection for given heat dissipation and surface area (available space). For example, for a heat dissipation of 10 [W] using a fin of diameter 20 [mm] and height 100 [mm], the expected increase in temperature of the base of fin is 10 [W] x 62.8 [cm2] x 0.1431 = 89.9 [K].
L | [mm] | 100.0 | 100.0 | 100.0 | 100.0 | 100.0 | 100.0 | 100.0 |
D | [mm] | 5.0 | 10.0 | 20.0 | 25.0 | 50.0 | 100.0 | 200.0 |
h | [W/m2-K] | 20.0 | 20.0 | 20.0 | 20.0 | 20.0 | 20.0 | 20.0 |
ΔT | [K] | 60.0 | 60.0 | 60.0 | 60.0 | 60.0 | 60.0 | 60.0 |
NF | [m] | 8.9 | 6.3 | 4.5 | 4.0 | 2.8 | 2.0 | 1.40 |
A | [cm2] | 15.7 | 31.4 | 62.8 | 78.5 | 157.1 | 314.2 | 628.3 |
Q | [W] | 1.270 | 3.008 | 6.673 | 8.533 | 17.905 | 36.725 | 74.409 |
ΔT/[A.Q] | [K/W/cm2] | 3.0070 | 0.6350 | 0.1431 | 0.0895 | 0.0213 | 0.0052 | 0.0013 |
Thermal Resistances
Refer to fischerelektronik.de/fileadmin/fischertemplates/download/Katalog/heatsinks.pdf for types of heat sinks and their thermal resistances. As per the document, the values indicated in the diagrams apply only for heatsinks with black anodised surface, mounted vertically and natural convection. Correction factors: natural surface: +10 to 15%, for horizontal mounting: +15 to 20%.The content on CFDyna.com is being constantly refined and improvised with on-the-job experience, testing, and training. Examples might be simplified to improve insight into the physics and basic understanding. Linked pages, articles, references, and examples are constantly reviewed to reduce errors, but we cannot warrant full correctness of all content.
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