• Thermal Management of Electronic Assemblies and Enclosures

Applications of CFD tools in PCB, Board-level and Chassis Level Thermal Simulations

Electronics Cooling

chip Cooling

There are vast range of applications of thermal simulations in electronics industry dealing with Printed Circuit Board (PCB). In addition to board and chassis level simulation, thermal management of data centres include specialized cooling methods like heat sinks, TEC (Thermo-Electric Cooling), heat pipes, PCM (Phase Change Material), heat spreaders...

Types of Simulations

  • PCB or Package Level: Detail modeling of copper traces, thermal vias and dielectric material inside the PCB panel.
  • Board Level: PCB modeled as simplified orthotropic thermal conductivity.
  • Chassis Level: Similar to board-level simulation, bigger in computational domain.
  • Rack Level such as in Data Centres: Most of the heat sources are modelled as lumped blocks.

Electronics Cooling

Construction Features on IC Packages

Die: It designates the piece of semiconductor on which all the active circuits lie. Dies are made of Silicon (110 – 150 W/m.K) or Gallium Arsenide (GaAs, 45 – 60 W/m.K) is used in special applications such as microwaves. The circuitry is present within a thin layer on one side only, known as active surface.

The Die is often attached to the substrate or the die pad by an adhesive known as the "die attach" which is made of an epoxy based compound having thickness 0.025 - 0.050 [mm] and thermal conductivity in the range 1 - 2 [W/m.K]. The semiconductor material of a die has a conductivity approaching that of a metal. If the active layer is assumed to generate constant power per unit area (an assumption that may not always be valid), the die will be practically isothermal. In practice, applications exist for which the heat flux varies significantly across the die, in which case a temperature gradient may exist on its active surface. For most packages, the thermal resistance offered by the die is small in comparison with that offered by the rest of the package. Referecnce: FloTHERM Pack User's Guide

Due to low thickness of the "die attach", it causes very little heat spreading. At the same time, it offers significant thermal resistance in out-of- the-plane direction due to its poor thermal conductivity value.

Die Pad or Die Flag: The Die is placed in insulated boxed often plastic packages, on a thin metal plate (made of copper and larger than the die) known as the die flag or die pad. It helps both in the manufacturing and thermal (heat dissipation) function. The metallic die flag acts as an effective heat spreader due to very high thermal conductivity of copper which can reduce the thermal resistance of a package by up to 15%.

Componenets of a Die

Bond wires, made of Gold or Aluminum having diameter of the order of 0.025 [mm], are characteristics of wire-bonded packages. The number of bond wires in an IC package are of same order as the number of external leads/pins. Excerpts from "FloTHERM Pack User's Guide": In most ceramic packages, a negligible portion of the heat from the Die flows to the substrate through the bond wires. However, in plastic packages this may not be the case. Bond wires play a significant role in the heat transfer within peripheral leaded packages such as the PQFP. In area-array plastic packages such as the PBGA, bond wires can be important, especially for a 2-layer substrate.

Componenets of an Integrated Circuit - IC Chip

Encapsulant: Also known as 'Overmold', it is an epoxy based compound with a thermal conductivity 0.6 - 0.7 [W/m.K].

Construction Detail of an Integrated Circuit - IC Chip

Thermal Resistance an Integrated Circuit - IC Chip

LED - Integrated Circuit - IC Chip

Reference: FloTHERM PACK User Guide

CBGA = Ceramic Ball Grid Array, PBGA = Plastic Ball Grid Array, TBGA: Tape Ball Grid Array, CPGA: Ceramic Pin Grid Array

Flip Chip CBGA

Bond Wire TBGA

Thermal conductivities: Alumina - 21 [W/m-K], Kovar - 17 [W/m-K], Typical encapsulant and elastomer material - 0.4 ~ 0.6 [W/m-K], Polyimide: 0.2 [W/m-K], 37Pb/63Sn solder: 50 [W/m-K]

Ceramic Pin Grid Arrays

The construction of an IC (Integrated Circuit) chip is not homogeneous in 3D space. The actual heat generating segment is made-up of silicon (with thermal conductivity of 96 [W/m-K]) which will be surrounded by an Encapusulant before being attached to a Printed Circuit Board. Hence, a thermal resistance of an IC package is specified by its manufacturers which is the measure of ability of the IC package to transfer heat generated by the IC (die) to the printed circuit board or the ambient.

In general, thermal resistance Θ or RTH = ΔT / P where P is power dissipation from the chip package in [W] and ΔT = TJ - TA.

TJ is the junction temperature and TA is the ambient temperature. In other words, the thermal resistance of an IC package is defined as the amount of heat generated or a rise in temperature when 1 [W] of power is dissipated in the IC. E.g. if an IC package generate 0.50 [W] with Junction-to-Ambient thermal resistance of 100 [K/W], the temerature of junction will rise by 0.5 [W] × 100 [K/W] = 50 [K] over the ambient. The construction of IC packages decides the thermal resistances: few types are Dual Inline Packages (DIP), Ceramic through-hole package, Plastic through-hole package, Plastic leaded chip carrier (PLCC), Quad Flat Package (QFP), Plastic dual construction surface mounte package, Thin small outline package (TSOP)...
  • ΘJA: also designated as RΘJA, it is the thermal resistance from Junction to Ambient, measured as [K/W]. Ambient is a generic term to thermal 'ground'. This value depends on the package design, PCB, and heat transfer modes (airflow, radiation). As per "Semiconductor and IC Package Thermal Metrics" by Texas Instruments, it is a measure of the thermal performance of an IC package mounted on a specific test coupon.

    The standard test conditions are specified by Joint Electron Device Engineering Council (JEDEC) such as JESD15-3: Two-Resistor Compact Thermal Model Guideline, JESD51: Methodology for the Thermal Measurement of Component Packages (Single Semiconductor Device) and JESD51-12: Guidelines for Reporting and Using Package Thermal Information.

  • ΘJC: also designated as RΘJC, it is the thermal resistance from Junction to Case where case is a specified point on the outside surface of the package. It depends on the thermal conductivity of package materials (the lead frame, mold compound, die attach adhesive) and on the specific package design (thickness of the die body and die attach, exposed pads and internal thermal vias). ΘJC considers only the resistance of heat flow paths to the surface of the package and hence represents only the conductive heat transfer path thermal resistance. EIA/JESD51-1 defines RΘJC as "the thermal resistance from the operating portion of a semiconductor device to outside surface of the package (case) closest to the chip mounting area when that same surface is properly heat sunk so as to minimize temperature variation across that surface".
  • ΘCA: it is the thermal resistance from Case to Ambient. Thus: ΘJA = ΘJC + ΘCA
  • ΨJB: junction-to-board thermal-characterization parameter and ΨJT: junction-to-top thermal-characterization parameters are the "characterization parameters" that measure temperature change between the junction temperature and the temperatures of the board and top of the package respectively. These are not thermal resistances in true sense though they are useful to estimate the junction temperature when the temperature on top of the package or the board and the power dissipation are known.

Excerpts from "Semiconductor and IC Package Thermal Metrics" by Texas Instruments: RΘJA is a variable function of not just the package, but of many other system level characteristics such as the design and layout of the PCB on which the part is mounted. In effect, the test board is a heat sink that is soldered to the leads of the device. Changing the design or configuration of the test board changes the efficiency of the heat sink and therefore the measured RθJA. In fact, in still-air JEDEC-defined RΘJA measurements, almost 70 ~ 95% of the power generated by the chip is dissipated from the test board, not from the surfaces of the package. Because a system board rarely approximates the test coupon used to determine RΘJA, application of ΘJA using

[TJ = TA + RΘJA × P]

results in extremely erroneous values.

The document further elaboarates: "In light of the fact that RΘJA is not a characteristic of the package by itself but of the package, PCB and other environmental factors, it is best used as a comparison of package thermal performance between different companies. For example, if TI reports an RΘJA of 40 [°C/W] or 40 [K/W] for a package compared to a competitor's value of 45 [K/W], the TI part will likely run 10% cooler in an application than the competitor's part."

Excerpts from "Thermal Design Basics" by Analog Devices: In ICs, one temperature reference point is always the device junction, taken to mean the hottest spot inside the chip operating within a given package. The other relevant reference point will be either TC - the case of the device, or TA - that of the surrounding air. This then leads in turn to the above mentioned individual thermal resistances ΘJC and ΘJA. Taking the most simple case first, ΘJA is the thermal resistance of a given device measured between its junction and the ambient air. This thermal resistance is most often used with small, relatively low power ICs such as op-amps, which often dissipate 1 [W] or less. Generally, ΘJA figures typical of op-amps and other small devices are on the order of 90-100 [°C/W] for a plastic 8-pin DIP package, as well as the better SOIC packages.

The list of standards related to thermal characterization of IC chips are:
  • JESD51: Methodology for the Thermal Measurement of Component Packages (Single Semiconductor Device)
  • JESD51-1: Integrated Circuit Thermal Measurement Method—Electrical Test Method (Single Semiconductor Device)
  • JESD51-2: Integrated Circuit Thermal Test Method Environmental Conditions—Natural Convection (Still Air)
  • JESD51-3: Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
  • JESD51-4: Thermal Test Chip Guideline (Wire Bond Type Chip)
  • JESD51-5: Extension of Thermal Test Board Standards for Packages with Direct Thermal Attachment Mechanisms
  • JESD51-6: Integrated Circuit Thermal Test Method Environmental Conditions—Forced Convection (Moving Air)
  • JESD51-7: High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
  • JESD51-8: Integrated Circuit Thermal Test Method Environmental Conditions—Junction-to-Board
  • JESD51-9: Test Boards for Area Array Surface Mount Package Thermal Measurements
  • JESD51-10: Test Boards for Through-Hole Perimeter Leaded Package Thermal Measurements
  • JEDEC51-12: Guidelines for Reporting and Using Electronic Package Thermal Information

Chip Construction Details

Some other examples are:

chip Package Architecture

chip Junction Temperature

Commercial Tools for thermal simulation

  • ANSYS ICEPAK: A customized GUI for pre- and post-processing but uses FLUENT as solver.
  • SIEMENS FloTHERM: similar in look and operation like ICEPAK with primitives, SmartPart and attributes.
  • Electrical Packages such as PSPICE and Cadence: These packages primarily meant for design of IC chips has thermal modeling capabilities to check 'what-if' scenarios.


Discrete power devices are the workhorses for power management and conversion of the most systems which fuel the central processing units and digital signal process ICs. Typical discrete products include various Diodes, Bipolars, metal-oxide-semiconductor field effect transistors (MOSFET) and Insulated Gate Bipolar Transistor (IGBT)s. A MOSFET may look like a black box from outside as shown below. However, inside the insulating enclusure contains many heat dissipating components consisting of silicon, copper and soldier joints. Capacitors and metal-oxide-silicon field effect transistors (MOSFETs) are the main elements in the ECU, which generate heat during operation, due to the Joule effect. In addition, capacitors and MOSFETs also generate heat due to electro-chemical reactions, dielectric losses and entropy changes.

MOSFET package

Reference: AN90003 - LFPAK MOSFET thermal design guide


  • Part number BUK7M15-60E (LFPAK33, 15 mΩ, 60 V) the maximum thermal resistance junction to mounting base is 2.43 [K/W], the total thermal resistance, junction-to-ambient is 59.4 [K/W] when using 65.4 °C as (ambient) reference point.
  • Part number BUK7S1R0-40H (LFPAK88, 1 mΩ, 40 V) the maximum thermal resistance junction to mounting base is 0.4 [K/W], the thermal resistance between mounting base and ambient is of much higher value (~ 30 K/W)

  • Power Density, PD: The power density of any device is the ratio of output power and the physical space it occupies. Thus, the unit of power density is [W/m3] or [W/cc].
  • Efficiency, η: This is the ratio of output power and the input power. The loss of energy (or power) gets converted into heat. Hence, when power density is increased, the volume and surface area of MOSFET and any such device will decrease. To keep temperature rise of the system within permissible limit, the amount of heat dissipation has to be decreased which in turn require that the efficiency of the device must be increased.
  • Heat dissipation: q = PIN - POUT = h x A x [TS - TAMB] where h is the convective heat transfer coefficient of the surface exposed to cooling media, A is the skin (fluid-wetted) surface area, TS is the surface temperature of the device casing and TAMB is the bulk mean temperature of cooling media.
  • Efficiency: η = POUT / PIN = POUT / [POUT + q]
  • η = 1 / [q/(V x PD) + 1] where V = volume of the device
  • η = 1 / [h x A x ΔT/(V x PD) + 1] where ΔT = [TS - TAMB]
  • Power Density of a MOSFET

MOSFET Cooling Arrangement

The conventional single side cooling 5x6mm MOSFET called SOP Advance (Figure 1) is covered with an insulating mold. Therefore, the heat dissipation path of the package is mainly its bottom drain side cooling plate.

the DSOP Advance package has a top source side cooling plate in addition to the bottom drain side plate as shown in Figure 2. These cooling plates contribute in reducing the thermal resistance (Rth).

Reference: TOSHIBA Technical Application Note

At thermal equilibrium, the maximum power dissipation PDMAX of a power MOSFET can be expressed in terms of the ambient temperature TA, the maximum channel temperature TCHMAX of the MOSFET and the channel-to-ambient thermal resistance RTHCH-A .

Equivalent thermal network of a MOSFET

  • θi: Internal thermal resistance (channel-to-package)
  • θb: External thermal resistance (package-to-ambient air), varies with the material and shape of the case and is significantly larger than θi, θc, θs and θf.
  • θs: Thermal resistance of insulation shield
  • θc: Contact thermal resistance (at the interface with a thermal fin)
  • θf: Thermal resistance of the heat sink
Since no heat sink is generally used for power MOSFETs in a thermally conductive package RTHCH-A can be calculated as RTHCH-A = θi + θb. Since θb >> [θc + θs + θf]:

Simplified Equivalent thermal network of a MOSFET

Reference: Numerical Study on Heat Transfer Characteristics of the 36V Electronic Control Unit System for an Electric Bicycle by Gihan Ekanayake, Mahesh Suresh Patil, Jae-Hyeong Seo and Moo-Yeon Lee.
Component Material Thermal Conductivity [W/m-K] Density Specific Heat Capacity [J/kg-K]
Capacitor Aluminium Oxide 30 3890 880
MOSFET Silicon 80 ~ 150* 2390 712
Thermal Grease SiC 0.42 2500 750
Remarkably, the thermal conductivity (in W/mK) defined in various papers and handbooks varies widely for pure Si.

MOSFET Thermal Network

Reference - [AN90003: LFPAK MOSFET thermal design guide] "The PCB material FR4 has a maximum operating temperature of around 130 [°C], depending on manufacturer and chemistry, this is much lower than the limit specified for the junction of a silicon die (175 °C)".


Some key features of such simulations are usage of Intermediate Data Format (IDF) and Incremental Data eXchange (IDX) files that have been exported from an ECAD package. These files contain informations of traces in PCB. In ANSYS ICEPAK, while importing traces the default materials are Cu-pure for metal and FR4 for dielectric. PCB construction is a layered design along the thickness direction and hence the thermal conductivity is necessarily orthotropic. Here, the conductivity value along the thickness direction - known as through-the-plane conductivity is far less than in-the-plane conductivity values.

There are many programs used to generate design of electronic items such as PCB and chips. Cadence, EasyEDA, Eagle, Altium Designer to name few. However, there is a need to have interface between ECAD and MCAD. This is accomplished by EMN and EMP files. The EMN file is related to the board and the EMP file is the library list of the components on the board. These files can generate a 3D view of the PCB Assembly. IDF files default to the following extensions: *.emn - neutral file of the board outline and component placement and *.emp - profile file that contains component outlines.

PWA = Printed Wiring Assemblies. Excerpts from "Intermediate Data Format Specification, Version 3.0": Structure of the Intermediate Data Format - The Intermediate Data Format consists of three files: the Board File, the Library File and the Panel File.

The Board File: It contains a description of a single PWA, including the board shape, layout restrictions and component placement.

The Library File: It contains descriptions of components used by one or more PWAs.

The Panel File: It contains a description of a manufacturing panel including the panel shape, layout restrictions and the placement of boards and components on the panel.

Data is organized by sections in these files. Each section begins with a keyword indicating the type of data the section contains and a matching keyword at the end of the section. All data between the section keyword and its corresponding ending keyword pertains to that section. Sections cannot be nested. Unless otherwise noted, sections within a file can be in any order. Data within the sections is represented by one or more records consisting of one or more fields. Each line in a file is a separate record: fields within a record are separated by one or more blanks. Records within a section and fields within a record must be in a specific order. Records are free format which means that the fields they contain can be any length, and each field can begin in any column as long as the order of fields is maintained.

The Panel File is an optional file, similar to the Board File, that contains the physical description of a manufacturing step-and-repeat panel and the locations of boards and components on that panel. The Panel File references one or more PWAs described in separate Board Files. Any component placed on the panel itself is referenced in a Library File.

The Gerber file

It is a connector and bridge between designers, engineers and PCB manufacturers. It needs to go through every manufacturing process and the factory can clearly define the customer's needs. According to UCAMCO (the company that currently owns the rights to Gerber File format): "Gerber file format" is a standard for PCB design data storage or transfer. Gerber file describes and communicates the constituents of a PCB image like the number of copper layers, solder masks and many others such attributes. Gerber files also act as input files to PCB printing devices like photo-plotters and Automated Optical Inspection (AOI) machines to print or compare circuit board images for different gadgets. Gerber files may also include metadata (data about other constituting data within a file) like solder mask, legend/silk and number of copper layers among other relevant printing information.

Following files comprized the full list of GERBER files which is usually zipped and shared to thermal simulation engineer or PCB Manufacturer.

Gerber File Type Extension
Top side (copper) Layer .GTL
Bottom side (copper) Layer .GBL
Top Overlay .GTO
Bottom Overlay .GBO
Top Paste Mask .GTP
Bottom Paste Mask .GBP
Top Solder Mask .GTS
Bottom Solder Mask .GBS
Keep-Out Layer .GKO
Drill Drawing .GD1
Drill Guide .GG1
Internal Plane Layer 1, 2 ... 16 .GP1, .GP2 ... .GP16

These softwares are meant for electronics industry only and hence contains lots of objects related to this applications to fasten the simulation process. They can be summarized as follows:

Electronic Cooling Software

  • Primitive - Fundamental geometric entities in FloTHERM and ICEPAK: Cuboids, Prisms and Flow Resistances
  • SmartPart - Object parametrically created out of Primitives: e.g. Enclosure, fan, PCB, cylinders, volume or surface heat source, heat sinks (described by base dimension, number of fins, fin width and fin height), perforated plate (fully designated by hole size and arrangement, pitch, free area ratio)
  • Assembly - A group of Primitives, SmartParts and Sub-Assemblies
  • Attribute - A property that can be attached to Primitives and SmartParts (e.g. material properties)
Primitives defined in ICEPAK

ICEPAK Primitives

Reading Mechanical CAD (MCAD) data
  • The MCAD data can be read either in their native format such as ProE, Solidworks or CATIA files (parts and assemblies) or neutral formats such as IGES, STEP or PARASOLID.
  • After initial defeaturing (removal of chamfers and fillets) and simplifications (removal of small holes, branding logos, part identifiers), the MCAD geometry needs to be converted into ICEPAK / FloTHERM entities.
  • Simplification is permissible to the to the extent where the geometry could be created manually using primitives and smart-parts in ICEPAK / FloTHERM!
  • The conversion into ICEPAK / FloTHERM entities is a process of replacing a detailed geometry say perforated plate with a plate of same size without perforation and specifying the perforation details as attributes to the ICEPAK / FloTHERM entities.

Mesh generation process and recommendations
  • For naturally convected cases, the computational domain needs to be made bigger than the chassis or the board.
  • For the space above the chassis extend the domain 2~3 × height of chassis. Note that the buoyancy may not be strong enough to establish a flow from lower face to upper face and reverse flow can be observed on both of these faces. In order to reduce the reverse flows, the domain boundaries may need to be kept closer to the heat source.
  • For space below chassis extend the domain equal to the height of chassis.
  • For the remaining sides (front, rear, left and right) of the chassis, extend the domain 0.5 ~ 1.0 × depth and width of the chassis.
  • In case on natural convection, the heat transfer through convection is low and hence radiation also contributed significantly. Up to 50% of heat transfer is by radiation and remaining 50% by natural convection.This can be justified by the fact that the HTC value for natural convection in air varies between 5~10 [W/m2.K] whereas equivalent HTC for radiative heat transfer = ε × σ × (TWALL4 - TAMB4) / (TWALL - TAMB) = 4.9 [W/m2.K] for ε = 0.5, TWALL = 100 [°C] and TAMB = 50 [°C].
  • The components are mostly represented as volume with sharp corners such as cuboid and rectangles. A cut-cell method also known as trimmer mesh or Cartesian mesh or snappyHexMesh (in OpenFOAM) is used in ICEPAK and FloTHERM.
  • For printed circuit boards as in any surface with a significant amount of heat flux, 3 cells in the first millimeter above the board (air volume) and 3 cells in the first millimeter below the board (solid volume) is recommended.
  • Maintain aspect ratio of cells < 100.
  • For fins, maintain > 5 cells cross a channel for better heat transfer and pressure drop prediction, use two or more cells across the thickness in the solid.

Special applications in Electronic Cooling
  • Thermo-Electric Cooling (TEC): This device is based on Peltier effect where thermal energy is absorbed at one dissimilar metal junction and discharged at the other junction when electric current flows within a closed circuit. It comprises of p-type and n-type semiconductors sandwiched between ceramic electrical insulators. TEC are solid state heat pumps for applications where cooling below ambient are required. The cold junction acts as 'evaporator' and hot junction as 'condenser' of a refrigeration cycle.

    TEC - Thermo-Electric Coolers

    • Seebeck Effect: ΔV = α × (TH - TC) where α [V/K] = differential Seebeck coefficient or (thermo electric power coefficient) between the two materials, positive when the direction of electric current is same as the direction of heat flow.
    • QH [W] = β [V] × I [A] where β is differential Peltier coefficient between given two materials
    • β < 0: Electric current and heat flow in opposite directions
    • β > 0: Electric current and heat flow in same directions
    • COP = coefficient of performance of the thermoelectric device = QC / J, which typically is between 0.4 and 0.7 for single stage applications.
  • Heat Pipe: Capillary effect and phase change (evaporation and condensation) are the phenomena which define operation of heat pipes. Due to phase change from liquid to vapour, the heat transfer coefficient for heat pipes is extremely high - of the order of 40,000 [W/m2.K]. Originally invented by NASA for space application, it has gained widespread application in electronics industry.

    Heat Pipe Section View

    Heat Pipe Appliction in CPU Cooling

  • Heat Spreader: This is an application similar to heat sink. The purpose of a heat spreader is to use material with a very high thermal conductivity such as graphite with k = 1400 [W/m-K] to make the heat flow in-plane over a larger area so that it can be further dissipated into ambient using heat sinks.
  • PCM - Phase Change Material: These are energy storage and release mechanism based on change of phase (typically solidification and melting). The material can be used to keep temperature fluctuations low in case of heating and cooling cycles. Sometimes, the PCM can also act as an insulator to heat dissipation based on thermal conductivity. Some key characteristics required for a energy storage and release type PCM are tabulated below.
    Characterisitcs Desired valueRemark
    Melting point, TMP As per temperature controlSelection of material will depend on temperature to be maintained
    Specific heat capacity, Cp HighEnergy storage capacity ∝ Cp. Higher the Cp, lesser the mass required to store a given amount of energy.
    Density, ρ HighEnergy storage capacity ∝ ρ and the volume required is also less as m = ρ * V
    Thermal Conductivity, k High for energy storage purposeLow value is required for insulation where heat is to be maintained near the source itself
    Coefficient of volume expansion, γ LowThis governs flexibility or void space required in the storage container
    Chemical compatibility Non-corrosiveShould not react with the container and other materials in case of leaks
    Thermal cycling (heating-cooling) stability No degradationThe micro-structure and material properties should not degrade with heating-cooling cycles

TEC Performance Calculation

Field Variables

  1. i = Current [A]
  2. k = Thermal conductivity of TEC block [W/m-K]
  3. QH = heat rejection from hot surface (the 'condenser') [W]
  4. QC = heat absorption by cold surface (the 'evaporator') [W]
  5. R = Electric Resistance of TEC assembly [Ω]
  6. TC = cold side temperature (the 'evaporator') [K]
  7. TH = hot side temperature (the 'condenser') [K]
  8. P = power consumption by TEC device = (QH - QL) [W]
  9. S = seebeck co-efficient [V/K]
  10. ΔT = temperature difference between hot and cold junction [K]
  11. G = Ratio of cross-section area to the length (thickness) of the device [m]
  12. ρ = resistivity of TEC device [Ω-m]
  13. COP = Coefficient of Performance = QC / P

TEC Analogy

QC = -[S.i.TC − 0.5 × i2R − k.×G×(TH − TC)], negative sign is for heat flow into the device.


QC = -[S.i.TC - 0.5 × i2ρ/G − k×G×(TH − TC)]


QH = [S.i.TH + 0.5 × i2R − k.×G×(TH − TC)]


QC = [S.i.TH + 0.5 × i2ρ/G − k×G×(TH − TC)]

TEC Temperature Profile

Anisotropic or Orthotropic Thermal Conductivity: The printed-circuit boards are formed by many layers of copper wires known as traces and dielectric material (say FR4). They are so thin that they cannot be modeled (meshed and boundary conditions applied) separately. Hence, the thermal conductivity of board can be simplified using equivalent uniformed value along the thickness and in-the-plane direction. This simplification is done using series and parallel arrangement of thermal resistances analogous to electrical resistances.

Orthotropic conductivity based on lumped block assumptions. 10% Copper is a reasonable guess

  • kIN_PLANE = VFCu × kCu + (1-VFCu) × kDie
  • 1/kX_PLANE = VFCu / kCu + (1-VFCu) / kDie
  • Here, VF = Volume Fraction of copper in fractions (that is the value lies between 0 and 1).
CFD mesh vs. background mesh:

PCB Background Mesh in ICEPAK

PCB Local Thermal Conductivity in ICEPAK

A bit more detailed calculation of thermal conductivity is layer-by-layer estimation also known as "Discrete Layer Stack-up". For each layer:

kLAYER_i = kCu × ACu / APCB + kFRP × AFRP / APCB

Discrete layer stack-up in PCB

A detailed calculation of effective thermal conductivities in X-, Y- and Z-directions can be estimated by spliting the PCB in smaller segements and using smaller patches as described below. This method is useful for capturing conduction paths near heat generating components and heat sinks.

detailed Thermal Conductivity PCB

detailed Thermal Conductivity X, Y, Z directions

Typical *.emn File Entry
#The comment character is the pound sign (#). A comment must be a separate line
#(record) and the comment character must be in column 1. Comments should be 
#located between, but not within sections of the IDF files.
BOARD_FILE 3.0 "Sample File Generator" 2020/07/01.16:02:44 1
sample_board THOU
#Unit MM or THOU = milli-inch
#MCAD - Outline is owned by the Mechanical system and should not be modified in
#the Electrical system
#ECAD - Outline is owned by the Electrical system and should not be modified in 
#the Mechanical system
#UNOWNED - Outline can be modified in either system
#62.0 is thickness in milli-inch
0 5030.5 -120.0  0.0
0 5187.5 -120.0  0.0
0 5187.5  130.0  0.0
0 5155.0  130.0  0.0
0 5155.0  550.0 -180.0
EthnetBrd 135792468 THOU 59.0
0 -92.0  63.0 0
0 -92.0 -63.0 0
0  92.0 -63.0 0
0  92.0  63.0 0
0 -92.0  63.0 0
EthnetBrd 135792468 E7
20.5 32.5 0.0 90.0 BOTTOM PLACED
  • EthnetBrd is the ECAD name
  • 135792468 is the ecad_alt_name (unique part number)
  • E7 is the reference designator
  • 20.5, 32.5 0.0 represent the location with respect to the origin of PCB (0,0) point X, Y, Z directions
  • 90.0 represents the orientation of the component
  • BOTTOM specifies the side of the PCB
  • PLACED specifies component will be added to 3D PCB

ICEPAK is a GUI for pre- and post-processing. It uses FLUENT as solver and in this process many files get created. Following is a list of files and its owner (ICEPAK or FLUENT?).

File Type Created by Used by Suffix / Filename Remark
Problem ICEPAK ICEPAK problem
Mesh inputICEPAK  meshergrid_inputInputs for the mesh generator.
Mesh outputmesherICEPAK grid_outputOutput from the mesh generator that is the mesh file
CaseICEPAK FLUENT .casContains all the information that is needed by ICEPAK to run the solver
DataFLUENT FLUENT .dat and .fdatFiles when it has finished calculating: *.dat and *.fdat. These data files can be used to restart the solver
ResidualFLUENT ICEPAK .resInformation about convergence monitors: Solve → Solution monitor or select Convergence plot in Post menu
ScriptICEPAK ICEPAK.SCRIPT or _sc.batRuns the solver executable and can also be used to run the solver in batch mode.
Solver inputICEPAK FLUENT .uns_inThe solver input file (projectname.uns_in) is read by the solver to start the calculation.
Solver outputFLUENT .uns_outInformation from solver that is displayed on screen during calculation - this file is written only on Linux systems
DiagnosticICEPAK .diagContains information about correspondence between object names in model file and object names in case file
OptimizationICEPAK optimizer.log, .dat, .tab, .post, .rptOptimization of field variables
PostprocessingFLUENTICEPAK .resdUsed by ICEPAK for post-processing. All solutions that exist for the current project are listed by solution ID.
GeometryExternalICEPAK.igs, .stp CAD geometry - input to ICEPAK
PackagedICEPAK ICEPAK.tzrProject archive

Few keyboard short-cuts and special topics in ICEPAK
  • Move legend with Ctrl and the middle mouse button
  • Edit levels and set orientation with shift right-click on legend
  • Move the cut-plane in the domain with shift and the middle mouse button
  • Shift middle-click on CAD objects to graphically move the CAD geometry
  • Thermal Chokepoint: the dot product of heat flux and temperature gradient - it shows regions of high heat flux experiencing large thermal resistances
  • Thermal Cross: the cross product of heat flux and temperature gradient - it shows regions where large heat flux vectors not aligned with high thermal gradients

Basic Solver Setting
Note that ICEPAK uses FLUENT in background as solver.

Solver Settings in ICEPAK

Mesh Generation
The default option in ICEPAK is to generate a Cartesian mesh similar to snappyHexMesh in OpenFOAM, trimmer mesh in STAR-CCM+

Mesh Generation Settings in ICEPAK

Mesh Display Settings in ICEPAK

Mesh Quality Check in ICEPAK

Fan, Fins and Grilles
There are many in-built feature to model flow resistances and momentum sources / sinks.

Types of Fans in ICEPAK

Fan swirl: tangential component of flow at exit of a fan.

Modeling of Fan Swirl in ICEPAK

Heat Sinks:

Fin Types in ICEPAK

Fins in ICEPAK

Fin Geometry in ICEPAK

Grilles and Louvres:

Grilles in ICEPAK

Boundary Conditions
Wall boundary condition:

Wall B.C. in ICEPAK

PCB Gerber File Import

pcb Import Gerber in ICEPAK

PCB Stack Data

pcb stack data in ICEPAK

PCB Stack-up Data in Detail

pcb geometry detailed input in ICEPAK

Monitors and Runs Settings

Monitor Points in ICEPAK

Solver Run Settings in ICEPAK

Cooling systems in the field of microelectronics and microelectromechanical systems (MEMS) use small and microscale flow passages. The transport phenomena in microscale channels are very different as compared to conventional size channels or macroscale channels. There are several dimensionless numbers used to represent the feature of fluid flow in microscale channels, similar to Reynolds number in macro-chnnels. The distinction between macro- and microscale channels may also be classified according to these dimensionless numbers.
Heat Transfers from Extended Surfaces (Fins)
This section provides a way to calculate heat transfer rate and estimate typical range of values for designs. Two design criteria used to define performance of fins are "fin efficiency" and "fin effectiveness". Fin efficiency is ratio of "actual heat transferred through fins" to the "heat that would be transferred if the entire fin were as base temperature".

Fins Plate Type

Such fins are extruded or machined and needs to be fixed on the heat generating component using adhesive or screws. This creates a thermal contact resistance and needs to be accounted for temperature calculation of the mating surfaces.
BFThickness of fins[mm]122255
LFHeight of fins[mm]202010202010
WFWidth of Al-fins[mm]250250250250100100
AFCross-section of fins[mm2]250500500500500500
PFPerimeter of fins[mm]502504504504210210
kFThermal conductivity of fin[W/m-K]100100100100100100
hConvective Heat Transfer Coefficient[W/m2-K]101010101010
NFFin parameter[m-1]14.1710.0410.0410.046.486.48
RFThermal resistance of each fin[K/W]10.2310.0519.9110.0523.9447.69
iFNumber of fins[nos]101010101010
RFThermal resistance of all fins[K/W]
ΔTTemperature potential[K]606060606060
QHeat transfer rate [W]58.759.730.159.725.112.6
AHeat transfer surface area[cm2]101051042
ΔT/[A.Q]Heat transfer rate [K/W/m2]0.1020.1010.3980.1010.5992.384

Fins Pin Type

Following calculations is valid for pin-type and plate-type fins only.
Select the type of Fin:
Thermal conductivity of fin in [W/m-K]:
Specify length or height of fin [mm]:
Diameter (pin-type) or thickness (plate-type) of fin [mm]:
Width of plate-type fin [mm]:
Convective HTC on fin surface [W/m2.K]:
Reference temperature [°C]:
Base temperature [°C]:
Base thickness [mm]:
Tip convection [W/m2.K]:

The heat transfer rate of pin-type fin for natural convection in air is tabulated below. Note the impact of L/D ratio on heat transfer rate.

L [mm] 100.0 100.0 100.0 100.0 100.0 100.0 100.0
D [mm] 5.0 10.0 20.0 25.0 50.0 100.0 200.0
h [W/m2-K] 10.0 10.0 10.0 10.0 10.0 10.0 10.0
ΔT [K] 60.0 60.0 60.0 60.0 60.0 60.0 60.0
NF [m-1] 8.9 6.3 4.5 4.0 2.8 2.0 1.40
A [cm2] 15.7 31.4 62.8 78.5 157.1 314.2 628.3
Q [W] 0.7520 1.6680 3.5370 4.4760 9.18 18.60 37.45
ΔT/[A.Q] [K/W/cm2] 5.079 1.145 0.270 0.1707 0.0416 0.0103 0.0025

The values for forced convection in air is tabulated below. 'A' is the heat transfer area of the fin and not the cross-section area. The parameter ΔT/[Q.A] can be used in fin selection for given heat dissipation and surface area (available space). For example, for a heat dissipation of 10 [W] using a fin of diameter 20 [mm] and height 100 [mm], the expected increase in temperature of the base of fin is 10 [W] x 62.8 [cm2] x 0.1431 = 89.9 [K].

L [mm] 100.0 100.0 100.0 100.0 100.0 100.0 100.0
D [mm] 5.0 10.0 20.0 25.0 50.0 100.0 200.0
h [W/m2-K] 20.0 20.0 20.0 20.0 20.0 20.0 20.0
ΔT [K] 60.0 60.0 60.0 60.0 60.0 60.0 60.0
NF [m] 8.9 6.3 4.5 4.0 2.8 2.0 1.40
A [cm2] 15.7 31.4 62.8 78.5 157.1 314.2 628.3
Q [W] 1.270 3.008 6.673 8.533 17.905 36.725 74.409
ΔT/[A.Q] [K/W/cm2] 3.0070 0.6350 0.1431 0.0895 0.0213 0.0052 0.0013

The chart below provides a comparison between two designs of circular fins. Here, L ≡ r2 - r1 and 'A' is based on section shaded in dark colour. Reference: A Textbook of Heat Transfer by Lienhard and Lienhard.

Circular disk fins

Triangular fins

Contact us
Disclaimers and Policies

The content on CFDyna.com is being constantly refined and improvised with on-the-job experience, testing, and training. Examples might be simplified to improve insight into the physics and basic understanding. Linked pages, articles, references, and examples are constantly reviewed to reduce errors, but we cannot warrant full correctness of all content.